(1) Field of the Invention
The present invention relates to methods of fabricating a metal-insulator-metal capacitor, and more particularly, to methods of forming metal-insulator-metal capacitors for embedded DRAM applications wherein contact etch depth is reduced in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
In merging logic circuits and dynamic random access memory (DRAM) arrays on a single chip, compatibility is the primary issue with respect to both design and fabrication. Recently, with the continued decrease in device dimensions, it has become increasingly important to find solutions to problems that are caused by etching high aspect ratio contact openings. The DRAM capacitor""s height must be increased in order to meet the high capacitance requirement. Meanwhile, in order to achieve a high dielectric constant for a metal-insulator-metal (MIM) or metal-insulator-silicon (MIS) capacitor, the dielectric material should be deposited at high temperature (of more than about 600xc2x0 C.) or annealed at high temperature after film deposition. Thus, the capacitor formation must be completed before the copper/low dielectric constant (k) material process. But this limitation will impact contact etching because of device dimension shrinkage. Because of the high capacitance requirement, the height of the capacitor cannot be reduced. However, we can try to improve the contact high aspect ratio etch problem in other ways. U.S. Pat. Nos. 6,096,597 to Tsu et al, 6,329,234B1 to Ma et al, and 6,271,084B1 to Tu et al show MIM capacitor processes. U.S. Pat. No. 6,211,061 to Chen et al teaches a dual damascene process with carbon-based low-k materials.
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor in an embedded DRAM process.
Another object of the present invention is to provide al method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process with reduced contact etch depth.
In accordance with the objects of this invention, a method for fabricating a metal-insulator-metal capacitor, in an embedded DRAM process is achieved. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.
Also in accordance with the objects of this invention, a method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is achieved. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in two twisted trench in a self-aligned copper process. The two twisted trenches are mirror images of each other wherein each capacitor in a first of the two twisted trenches is horizontally aligned with a capacitor in the second of the two twisted trenches to form pairs of capacitors wherein the pairs of capacitors are separated from each other horizontally by a first or a second distance wherein the first distance is greater than the second distance. The capacitors are formed by the following process. A silicon carbide layer is deposited overlying the contact plugs. A low dielectric constant material layer is deposited overlying the silicon carbide layer. A stop layer is deposited overlying the low dielectric constant material layer. A first opening is formed through the stop layer, the low dielectric constant material layer, the silicon carbide layer, and the insulating layer to the node contact plug. A first metal layer is deposited overlying the stop layer and within the first opening. The first opening is filled with a sacrificial layer which is etched back to leave the first metal layer only within the first opening and recessed from the top of the first opening wherein the first metal layer forms a bottom electrode of the capacitor. Thereafter, the sacrificial layer and the stop layer are removed. A twisted trench is formed. A capacitor dielectric layer is deposited overlying the bottom electrode. A second metal layer is deposited overlying the capacitor dielectric layer. A third metal layer is deposited overlying the second metal layer and filling the first opening. The third metal layer, the second metal layer, and the capacitor dielectric layer are polished back to leave these layers only within the first opening wherein the second and third metal layers together form a top electrode of the capacitor. Second openings are etched through the low dielectric constant layer and the silicon carbide layer to the contact plugs. The second opening in the memory area lies between the two twisted trenches and in a horizontal line with one capacitor pair having the first separation distance wherein adjacent capacitor pairs have the second separation distance. The second openings are filled with a fourth metal layer to complete contacts to the contact plugs in the logic area and in the memory area.
Also in accordance with the objects of the invention, an improved embedded DRAM and capacitor structure device is achieved. Trenched capacitors are formed in two twisted trenches through an insulating layer in a memory area of an integrated circuit wherein the two twisted trenches are mirror images of each other and wherein each capacitor in a first of the two twisted trenches is horizontally aligned with a capacitor in a second of the two twisted trenches to form pairs of capacitors wherein the pairs of capacitors are separated from each other horizontally by a first or a second distance wherein the first distance is greater than the second distance. A bit line contact in the memory area through the insulating layer to a bit line lies between the two twisted trenches and in a horizontal line with one capacitor pair having the first separation distance wherein adjacent capacitor pairs have the second separation distance. First line metal contacts are formed in a logic area of the integrated circuit. The bit line contact and the first line metal contacts are no higher vertically than the trenched capacitors.